1. Field of the Invention
The invention generally relates to a method for fabricating a semiconductor structure, and more particularly, to a method for fabricating a semiconductor structure with a staircase structure.
2. Description of Related Art
Following the integration of semiconductor devices, in order to achieve high density and high performance, developments towards three-dimensional space have become the trend under the condition of having a limited unit area. Using a non-volatile memory as an example, it includes a vertical memory array formed by a plurality of memory cells. Even though the three-dimensional semiconductor device enables memory capacity per unit area to increase, but also raises the difficulty for elements in different layers to connect with each other.
In recent year, pad with a staircase structure have been developed in the three-dimensional semiconductor device. The pad can enable the elements located at each layer to be easily connected with the other elements. However, defining a staircase, for example, requires to undergo one time of a lithography and etching process. As the layer of the three-dimensional semiconductor device increases, defining a plurality of staircases then requires to undergo multiple times of the lithography and etching process, thus not only increasing the production costs but also seriously affect the productivity. Therefore, how to simplify the fabrication process of the staircase structure in the three-dimensional semiconductor device, so as to lower the production costs, is a current topic that needs to be researched.